To match up with well-developed IC fabrication processes (e.g., 0.13 μm processes) for application specific integrated circuit (ASIC) and system-on-chip (SoC) circuitry designs, wafer manufacturers are introducing new materials and manufacturing techniques in order to produce smaller integrated circuits with faster speeds. However, accompanied with smaller process scales, scaled thresholds and unscaled voltages, issues of more severe current leakage and static power consumption have arisen.
For IC manufacturing processes of, e.g., 90 μm and below 65 μm, power management stands as a crucial factor that is looked into during the design process. To effectively respond to difficulties in power management, various techniques including multi-threshold, multi-voltage, clock gating and power gating have been adopted for reducing static power consumption of circuits.
A power gating circuit of a mobile device is generally provided with MTCMOS transistors consisted of a positive channel metal-oxide-semiconductor (PMOS) or a negative channel metal-oxide semiconductor (NMOS). An MTCMOS transistor accomplishes power gating by separating constant VDD and switched VDD to turn off functions module that are temporarily idle in the mobile device so as to noticeably reduce static power consumption.
FIGS. 1A and 1B respectively show schematic diagrams of two different power gating circuits. As shown, a power gating circuit 1 comprises a PMOS component 10 and a power gating circuit 1′ comprises a PMOS components 11 and 12, and both circuits comprise both a constant VDD and a switched VDD.
Refer to FIGS. 2A and 2B respective showing a schematic diagram of a circuit layout of a common power gating circuit, which includes the layout of a gate terminal G, source terminal S, drain terminal D, and a sectional diagram of an MTCMOS transistor 20 obtained along a dotted line L in FIG. 2. It is observed from FIG. 2B that, the MTCMOS transistor 20 accomplishes power gating by separating the constant VDD and the switched VDD; that is, there is no coupling between the constant VDD and the switched VDD, and such absence of coupling results in complications for static IR (voltage) drop of the MTCMOS 20.
Static IR (voltage) drop of an MTCMOS transistor can be analyzed by Electronic Design Automation (EDA) tools, which are quite costly and a heavy burden on IC designers or IC manufacturers.
Therefore, it is an objective of the invention to provide a static IR (voltage) drop analyzing apparatus and associated method for solving the foregoing issue.